Video digital data typically originates in parallel form, but is recorded in serial form. The serial data is then reconstituted in its parallel form during playback. Sync patterns, strings of bits in a predetermined sequence embedded in the serial data at regular intervals, serve as keys for dividing the serial data into the same bytes of parallel bits which constituted the original parallel data. This process may also be conceptualized as the alignment of the byte boundaries with their original positions.
Two phenomena are known to interfere with the proper alignment of the reconstituted parallel data with the original parallel data. The first such phenomenon is the tendency of the sync pattern to "slip," that is, to occur either slightly before or after the end of the normal interval between sync patterns, typically due to "dropouts" occurring between sync patterns. It is therefore desirable that a sync detection circuit be able to recognize a sync pattern despite Bit slippage within an acceptable range to avoid loss of video data.
The other phenomenon is the erroneous failure of any recognizable sync pattern to occur at all at the beginning of a block, typically due to errors or dropouts occurring in the vicinity of the sync pattern. It is possible that video data is still present despite the absence of one or even several sync patterns. It is therefore desirable to provide a sync detection circuit which can continue to operate normally despite a failure to detect a sync pattern for a predetermined period of time after the normal interval between sync pulses.
It is further the case that conventional sync detection circuitry generally operates at a serial data rate rather than at a slower parallel data rate. Such circuitry therefore typically requires high-speed logic which in turn requires more power, and is less suitable for LSI integration, than logic adapted to operate at a slower parallel clock rate. It is therefore also desirable to provide a sync detection circuit in which most if not all of the circuitry operates at a parallel clock rate.
Toward this end, it is known as a first step to convert the incoming serial data to parallel data words without regard to proper alignment. Sync detection is then performed upon the parallel data at the parallel clock rate. A device such as a funnel shifter then shifts the parallel data into its original alignment using the position of the detected sync pattern as a guide. Such a system is disclosed, for example, in U.S. Pat. No. 4,414,677. The particular technique disclosed in this patent, however, involves identifying various repeating patterns spaced at one block intervals. This requires a substantial amount of memory (typically four or more sync blocks long) to retain data while a sync signal is sought. It is also necessarily dependent on the assumption that sync patterns will be equally spaced in the data stream, so that it cannot utilize "preamble" sync patterns, occurring at intervals shorter than normal blocks, to increase the reliability of detecting the first data sync block of a sector recorded on tape.
U.S Pat. No. 4,646,328 discloses a sync detection scheme in which data is processed at one third the serial byte rate, thus reducing the need for high speed logic. The basic approach, however, appears unsuitable for processing at any other rate. The technique disclosed in this patent is therefore probably not suitable for DVTR, where data is typically organized in 8-bit bytes.
U.S. Pat. No. 4,680,766 discloses a system for decoding and checking a sync block address. This effort is necessitated by the use of a data format which requires that the address be decoded independently with very high reliability to decode the rest of the block. Implementing this scheme requires three separate funnel or barrel shifters.